1. Field of the Invention
The present invention generally relates to nonvolatile semiconductor memory devices, and particularly relates to a method of and a circuit for writing data in a nonvolatile semiconductor memory device.
2. Description of the Related Art
When data are written in memory cells of nonvolatile semiconductor memory devices through program operations, charge is injected into the gates of memory cell transistors, resulting in increased thresholds. As a result, an electric current does not flow when a potential lower than these thresholds is applied to the gates. This achieves a data state that data xe2x80x9c0xe2x80x9d is written. In general, thresholds of memory cells in the erased state have variation. When programming is performed by applying predetermined write potentials to bring the thresholds above a verify level, thresholds of the memory cells after programming will also have some variation above the verify level.
There are nonvolatile semiconductor memory devices that represent multi-level values by setting memory cells to different thresholds. In such nonvolatile semiconductor memory devices, it is difficult to ensure reliable data recording if the distribution of thresholds is broad. This is because the gaps between adjacent data levels become narrower as the distribution broadens.
FIG. 1 is a flowchart showing a related-art operation that writes data in multi-level memory cells. FIG. 1 corresponds to a case in which the multi-values are comprised of 4 levels. FIG. 2 is an illustrative drawing showing bit distributions that are obtained after the completion of writing of memory cells according to the flowchart of FIG. 1. The horizontal axis represents the threshold of memory cell transistors, and the vertical axis corresponds to the number of bits (i.e., the number of memory cells). As shown in FIG. 2, there are four levels Erase, Level0, Level1, and Level2 after writing.
In order to write data at the four different levels, at step ST1, data is loaded to a page buffer. At a step ST2, data is stored in a write buffer WB with respect to memory cells that are subjected to Level2 writing. At step ST3, the memory cells that are subjected to writing are programmed by using potential pulses corresponding to Level2. At step ST4, a check is made as to whether the thresholds were shifted to Level2. At step ST5, a check is made as to whether all the bits subjected to writing have passed the check. If they have not yet passed, the procedure goes back to step ST3, followed by repeating the program and check operations. If all the bits subjected to writing have passed, the programming procedure for Level2 comes to an end, giving way to a next programming procedure.
At step ST6, data is stored in the write buffer WB with respect to memory cells that are subjected to Level0 and Level1 writing. At step ST7, the memory cells that are subjected to writing are programmed by using potential pulses corresponding to Level0. At step ST8, a check is made as to whether the thresholds were shifted to Level0. At step ST9, a check is made as to whether all the bits subjected to writing have passed the check. If they have not yet passed, the procedure goes back to step ST7, followed by repeating the program and check operations. If all the bits subjected to writing have passed, the programming procedure for Level0 comes to an end, giving way to a next programming procedure.
At step ST10, data is stored in the write buffer WB with respect to memory cells that are subjected to Level1 writing. At step ST11, the memory cells that are subjected to writing are programmed by using potential pulses corresponding to Level1. At step ST12, a check is made as to whether the thresholds were shifted to Level1. At step ST13, a check is made as to whether all the bits subjected to writing have passed the check. If they have not yet passed, the procedure goes back to step ST11, followed by repeating the program and check operations. If all the bits subjected to writing have passed, the programming procedure for Level1 comes to an end, which marks the end of the entire writing procedure.
When data writing is performed through programming, some cells are programmed earlier than other cells. That is, data writing is not yet completed with respect to these other cells at the time when the earlier cells are being programmed. There are thus a larger number of erased memory cells at such a time than when all the writing procedure is completed. When a currently selected memory cell is being verified, a large amount of an electric current flows into the ground potential through a large number of erased memory cells that are connected to the same word line as that of the currently selected memory cell. This results in a source potential of the memory cell being raised by the connect-line resistance, thereby letting the memory cell pass the verify check while its threshold still remains lower than a desired threshold.
In this manner, the state of memory cells connected to the same word line at the time of programming is different from the state of the memory cells at the time of data reading, and, thus, the raised level of the source potential is also different. This may cause an error in data reading.
In the writing procedure as shown in FIG. 1, the distributions of thresholds for Level0 through Level2 end up having their lower boundaries shifted to further left than the desired thresholds that are shown by hatches. This is caused by the same reasons as described above. Namely, passing the verify check at a threshold lower than a desired threshold causes the distributions of thresholds being broadened at their lower ends.
When programming for Level2 is performed in particular, data writing for Level0 and Level1 is not yet carried out, so that a quite large number of erased memory cells are in existence, compared to when the entire data writing is completed. As a result, the source potential of memory cells are significantly raised at the time of Level2 verify operation, compared to the time of data reading. This causes memory-cell thresholds to pass the verify check while they are lower than the desired threshold. The distribution of thresholds is thus broadened at its lower end.
When programming for Level0 is performed, data writing that raises thresholds to Level1 with respect to memory cells subjected to Level1 writing is not yet performed, so that a large number of erased memory cells are present, compared to when the entire data writing is completed. The distribution of thresholds is thus broadened at its lower end in the same manner as described above.
In the case of nonvolatile semiconductor memory devices that represent multi-values by setting the thresholds of memory cells to different threshold levels, a broadened threshold distribution as described above shortens an interval between adjacent data levels. This makes it difficult to achieve reliable data recording.
Accordingly, there is a need for a nonvolatile semiconductor memory device that achieves a sufficiently narrow distribution of thresholds after data writing.
It is a general object of the present invention to provide a nonvolatile semiconductor memory device that substantially obviates one or more problems caused by the limitations and disadvantages of the related art.
Features and advantages of the present invention will be presented in the description which follows, and in part will become apparent from the description and the accompanying drawings, or may be learned by practice of the invention according to the teachings provided in the description. Objects as well as other features and advantages of the present invention will be realized and attained by a nonvolatile semiconductor memory device particularly pointed out in the specification in such full, clear, concise, and exact terms as to enable a person having ordinary skill in the art to practice the invention.
To achieve these and other advantages in accordance with the purpose of the invention, the invention provides a nonvolatile semiconductor memory device, including a memory core circuit which is nonvolatile and stores multi-values therein by setting different thresholds to memory cells, and a control circuit which controls data writing into the memory core circuit, wherein the control circuit programs first memory cells to be at one of the thresholds by setting the one of the thresholds not only to the first memory cells but also to second memory cells that are subsequently to be programmed to any one of the thresholds higher than the one of the thresholds, the control circuit successively performing programming in an ascending order of the thresholds.
In the nonvolatile semiconductor memory device as described above, when program and verify operations are carried out in respect of a given threshold, writing in respect of any thresholds lower than the given threshold has already been completed. The memory cells are therefore placed in the same or similar program conditions as the memory cells observed at the time of data reading that will be performed after data writing. As a result, an increase in the source potential of the memory cells becomes substantially the same as an increase observed at the time of data reading, so that thresholds are set substantially equal to a desired threshold. The distribution of thresholds is not broadened at its lower end as was in the related art, and a sufficient interval between adjacent thresholds is secured, thereby achieving reliable data recording.
According to another aspect of the present invention, a nonvolatile semiconductor memory device includes a memory core circuit which includes nonvolatile memory cells, and a control circuit which controls data writing into the memory core circuit, wherein, in order to program given memory cells to be at a given threshold, the control circuit first programs the given memory cells by use of predetermined programming pulses and by use of a threshold lower than the given threshold for a verify purpose, and then programs the given memory cells by use of programming pulses weaker than the predetermined programming pulses and by use of the given threshold for a verify purpose.
In the nonvolatile semiconductor memory device as described above, the distribution of memory cells subjected to data writing has its upper end first defined through a verify check that uses a reference level lower than the given threshold. The lower end of the distribution is then shifted up by using relatively low potential pulses for the programming purpose and by performing a verify check that uses a reference level equal to the given threshold. Because of this procedure, the distribution ends up being narrower, compared to when a verify check is made throughout the procedure by using only the reference level equal to the given threshold.
Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.